Andreas T Jonsson
bf30c1eb6f
Replace the 80186 instruction set extension with full NEC V20 support: - Rename cpu_186.c to cpu_v20.c and add cpu_cycles.c/h for per-CPU cycle lookup tables indexed by opcode - Change CPU type from bitmask options to vxt_cpu_type_t enum (VXT_CPU_8088 / VXT_CPU_V20) - Add V20-specific instructions: TEST1/CLR1/SET1/NOT1, ROL4/ROR4, ADD4S/SUB4S/CMP4S, INS/EXT, REPNC/REPC - Update IDIV to ignore REP prefix quirk on V20 - Update test infrastructure and docs for V20 nomenclature
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References
A curated list of technical references useful for developing and understanding this project.
VirtualXT Repository (Git History & Past Releases)
The project's own repository is a valuable reference for how to write an emulator in different programming languages. The key insight is in the git history and past releases — the project has evolved through multiple language implementations over time. By examining previous releases and the commit history, you can see how the emulator was designed and built in each language, what trade-offs were made, and how the architecture changed between rewrites. Refer to this when looking for real-world examples of emulator implementation patterns across languages, or when considering how to approach a rewrite or port.
The PC Emulation Book (MartyPC)
A comprehensive guide to emulating the original IBM PC models (5150 and 5160/XT), written by the author of the MartyPC emulator. Covers hardware architecture, Intel 8088 CPU emulation, support chips (8253 timer, 8259 PIC), peripheral devices, keyboards, and system integration. Still under construction, but already has detailed pages on several key components. Refer to this when implementing or debugging specific hardware components, understanding how the original IBM PC system design works, or when you need detailed technical explanations of chip behavior and component interactions.
Minus Zero Degrees (-0°)
An extensive hardware reference site for the IBM 51xx PC family of vintage computers (5150 PC, 5160 XT, 5170 AT, and related models). Contains detailed information on motherboard revisions, BIOS versions, switch/jumper settings, POST sequences, power supplies, RAM, floppy and hard drive support, expansion cards, memory maps, and much more. Also hosts ROM images, documentation on MDA/CGA/EGA video modes, serial ports, and diagnostic tools. Refer to this when you need precise hardware details about the real IBM PC — such as BIOS behavior, POST error codes, motherboard diagrams, memory layout, or the specific differences between PC models and revisions. Invaluable for getting emulation behavior to match real hardware.
X86 Opcode and Instruction Reference
A compact, single-page x86 opcode and instruction reference table (coder32 edition). Lists every one-byte and two-byte opcode with its mnemonic, operands, affected flags (tested, modified, defined, undefined), processor requirements, and brief descriptions. Also available in other editions: coder64, geek32, geek64, etc. Includes ModR/M and SIB byte decoding tables. Refer to this when implementing or debugging CPU instruction decoding — it provides a quick way to look up opcode encodings, operand formats, and flag behavior without sifting through Intel's full manuals.
Felix Cloutier's x86 and amd64 Instruction Reference
A web-friendly, per-instruction reference derived from the Intel 64 and IA-32 Architectures Software Developer's Manual. Each instruction has its own page with detailed descriptions, operation pseudocode, affected flags, encoding tables, and exceptions. Covers core instructions, FPU, SSE, AVX, and more. Refer to this when you need the full specification of a particular instruction — its exact behavior, operand encodings, flag effects, and exception conditions. More readable than the raw Intel SDM for quick lookups of individual instructions. Note the site's own disclaimer: it is mechanically extracted and may not be perfect, so cross-reference with the official Intel SDM for critical details.
OSDev Wiki
A community-maintained wiki with 755+ articles covering OS and low-level systems development. Contains detailed pages on x86 CPU modes, interrupts, PIC, PIT, DMA, keyboard input, VGA hardware, ATA storage, filesystems (FAT, ext2), memory management, bootloaders, and much more. A go-to resource for understanding how PC hardware interfaces work at the programming level. Important caveat: much of the information on OSDev Wiki focuses on the IBM AT generation (286+) and later hardware. When working on PC/XT (8088/8086) emulation, pay close attention to whether a given article's details actually apply to the earlier PC/XT platform — differences in interrupt controllers, DMA, memory maps, and BIOS behavior can be significant.
8086 Microcode Disassembled (Reenigne Blog)
A detailed reverse-engineering of the 8086/8088 microcode ROM, extracted from die photographs by Andrew Jenner. Documents the complete microcode instruction set, the translation ROM that maps opcodes to microcode positions, and how each x86 instruction is broken down into micro-operations internally. Covers the differences between 8086 and 8088 microcode, which instructions are handled by microcode vs. random logic, effective address computation, interrupt handling, string instruction bugs/fixes, and even undocumented behaviors (e.g., REP MUL negates the result). The comment section is also valuable, with contributions from other researchers working on cycle-exact emulators and hardware reimplementations. Refer to this when you need to understand the internal timing and sequencing of 8086/8088 instructions at the microcode level, or when debugging cycle-accuracy issues in the CPU emulation.
The Complete Bus Logic of the Intel 8088 (MartyPC Blog)
A deep technical article by the author of the MartyPC emulator that fundamentally revises the accepted model of the 8088's bus cycle timing. Demonstrates that the 8088 actually has a 7-cycle (not 4-cycle) internal bus cycle, with pipelined address calculation stages (Tr, Ts, T0) that precede the four externally visible T-states (T1-T4). Explains previously mysterious bus "delays" — including prefetch abort penalties, SUSPEND delays, queue-full delays, and prefetch policy decisions — as natural consequences of the full bus cycle pipeline. Also covers interrupt timing (including the effect of the NXT microcode flag), wait states, HALT behavior, and the REP MOVSW vs REP MOVSB performance difference. Refer to this when implementing or debugging cycle-accurate 8088 bus timing, prefetch queue behavior, or when bus-related delays in your emulation don't match real hardware. The entire MartyPC blog is also worth browsing for related articles on the 8088 prefetch algorithm, CGA emulation, and floppy copy protection.
Exploring the NEC V20 CPU (MartyPC Blog)
An in-depth technical exploration of the NEC V20 CPU, an enhanced clone of the Intel 8088 that was both faster and added new instructions. The article covers the V20's internal architecture, its differences from the 8088, and the new instructions it introduced. Refer to this when working with NEC V20-specific features or when comparing V20 behavior against the Intel 8088.
NEC V20/V30 User's Manual
The official NEC V20/V30 User's Manual (1984). Contains detailed instruction reference tables, cycle timing charts, pinout diagrams, and electrical characteristics. The instruction reference covers all V20-specific opcodes including the bit-manipulation instructions (TEST1/CLR1/SET1/NOT1), nibble rotation (ROL4/ROR4), BCD string operations (ADD4S/SUB4S/CMP4S), and the extended I/O instructions (INS/EXT). Refer to this when implementing V20 extended opcodes or when you need authoritative cycle counts for V20 instructions.
VirtualXT V20 Hardware Test Suite
A repository of hardware-validated MOO test files for the NEC V20 CPU. Tests are generated on real V20 silicon and cover both 8088-compatible opcodes (arch: "86") and V20-specific instructions (arch: "186", "v30"). Used to verify VirtualXT's V20 emulation against real hardware. Refer to this when validating V20 instruction behavior, flag effects, or cycle timing, or when adding new V20-specific opcodes to the emulator.
CGA Notes (SEASIP)
A detailed reference on IBM's original Colour Graphics Adapter (CGA) and its clones. Covers hardware overview (MC6845 CRTC, character ROM, ISA bus resources, connectors, headers), memory maps for text and graphics modes, register I/O (mode control at 03D8h, colour control at 03D9h, status register at 03DAh), BIOS-supported and undocumented video modes (including the 160x200 composite colour mode and 160x100 text trick), and differences in CGA clones and successors (3270 PC, Professional Graphics Controller, Plantronics ColorPlus, Amstrad PC1512, PPC/PC20, Olivetti M24, Olivetti Prodest PC1, Compaq Portable/Deskpro, and Tecmar Graphics Master). Refer to this when implementing or debugging CGA video emulation, understanding CGA register behavior, memory layout, mode switching, or dealing with CGA-compatible clone hardware quirks.
Reconstructing the EGA BIOS (OS/2 Museum)
A blog post by Michal Necasek detailing the reconstruction of the IBM EGA BIOS from the published listings in the IBM Technical Reference. The reconstructed source code is available for download or online browsing. The article explains how the EGA BIOS uses video parameter/save tables, the dynamic save area for palette registers (most EGA registers were write-only), the role of the BDA pointer at 40:A8 during mode sets, and how font and mode overrides work. Also covers EGA monitor-type detection (MDA, CGA, or EGA monitor) and how it restricts available text and graphics modes at runtime. Refer to this when implementing or debugging EGA/VGA video BIOS emulation — especially the INT 10h mode set logic, parameter table handling, and palette state management. The reconstructed source itself is an authoritative reference for how the IBM EGA BIOS actually works internally.
HelpPC Interrupt Services Reference
A comprehensive quick-reference for IBM PC/XT/AT BIOS, DOS, EMS, and mouse interrupt services. Provides per-function documentation for all major software interrupts: INT 10h (video), INT 13h (disk), INT 14h (serial), INT 15h (system services), INT 16h (keyboard), INT 17h (printer), INT 1Ah (clock), INT 21h (DOS services with dozens of sub-functions including file I/O, memory management, IOCTL, and process control), INT 33h (mouse), and INT 67h (EMS). Also covers hardware interrupts (IRQ handlers INT 8, INT 9, INT 70h), the full interrupt vector table, exception vectors, and ancillary interrupts (INT 1Bh Ctrl-Break, INT 1Ch user timer tick, INT 1Dh video parameter table, INT 1Eh disk parameter table, INT 1Fh graphics character table). Each function page lists register inputs, outputs, and version-specific notes. Originally part of the HelpPC 2.10 reference by David Jurgens. Refer to this when implementing or debugging BIOS and DOS interrupt handlers — it provides a fast, encyclopedic lookup of expected register conventions and return values for every standard interrupt service function.
Intel 8088 Opcode Map (Pastraiser)
A single-page, color-coded opcode map for the Intel 8088 instruction set. Presents all 256 primary opcodes in a 16×16 grid with instruction mnemonics, byte lengths, cycle counts, and affected flags at a glance. Also includes tables for ModR/M group instructions (ALU, ROT, MISC, MOV, POP), the ModR/M effective address calculation modes with their extra byte counts and cycle costs, and a legend for the color-coding scheme (arithmetic/logical, load/store/move, jumps/calls, string instructions, prefixes, control, and group opcodes). Covers undocumented opcodes (marked with asterisks) such as POP CS, SALC, and the 0x82 ALU group alias. Refer to this when you need a quick visual lookup of 8088 opcode encodings, instruction sizes, cycle timings, or flag effects — particularly useful during CPU instruction decode implementation and debugging. Notably, this reference includes estimated cycle counts for every opcode, making it a handy quick-reference when implementing or verifying instruction timing in the CPU emulation.